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SAMOS III -- Reconfigurable Computing |
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The Molen Programming Paradigm |
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1 | (10) |
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Loading ρμ-Code: Design Considerations |
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11 | (9) |
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RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems |
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20 | (10) |
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Basic OS Support for Distributed Reconfigurable Hardware |
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30 | (9) |
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A Cost-Efficient RISC Processor Platform for Real Time Audio Applications |
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39 | (10) |
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Customising Processors: Design-Time and Run-Time Opportunities |
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49 | (10) |
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Intermediate Level Components for Reconfigurable Platforms |
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59 | (10) |
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Performance Estimation of Streaming Media Applications for Reconfigurable Platforms |
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69 | (9) |
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SAMOS III -- Architectures and Implementation |
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CoDeL: Automatically Synthesizing Network Interface Controllers |
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78 | (10) |
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Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units |
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88 | (10) |
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An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs |
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98 | (10) |
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Register-Based Permutation Networks for Stride Permutations |
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108 | (10) |
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A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures |
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118 | (10) |
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Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability |
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128 | (10) |
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Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs |
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138 | (11) |
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SAMOS III -- Compilers, System Modeling, and Simulation |
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Comparison of Data Dependence Analysis Tests |
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149 | (10) |
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Mouse: A Shortcut from Matlab Source to SIMD DSP Assembly Code |
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159 | (9) |
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High-Level Energy Estimation for ARM-Based SOCs |
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168 | (10) |
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IDF Models for Trace Transformations: A Case Study in Computational Refinement |
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178 | (13) |
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Systems, Architectures, Modeling, and Simulation 2004 (SAMOS IV) |
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Programming Extremely Flexible Platforms |
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191 | (1) |
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SAMOS IV -- Reconfigurable Computing |
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The Virtex II Pro™ MOLEN Processor |
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192 | (11) |
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Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements |
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203 | (10) |
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Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques |
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213 | (11) |
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Modeling Loop Unrolling: Approaches and Open Issues |
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224 | (10) |
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Self-loop Pipelining and Reconfigurable Dataflow Arrays |
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234 | (10) |
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Architecture Exploration for 3G Telephony Applications Using a Hardware---Software Prototyping Platform |
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244 | (10) |
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Embedded Context Aware Hardware Component Generation for Dataflow System Exploration |
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254 | (10) |
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On the (Re-)Use of IP-Components in Re-configurable Platforms |
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264 | (10) |
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Customising Hardware Designs for Elliptic Curve Cryptography |
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274 | (10) |
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Dynamic Hardware Reconfigurations: Performance Impact for MPEG2 |
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284 | (9) |
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Compiler and System Techniques for SoC Distributed Reconfigurable Accelerators |
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293 | (10) |
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SAMOS IV -- Architectures and Implementation |
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Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications |
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303 | (10) |
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On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering |
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313 | (10) |
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Memory Bandwidth Requirements of Tile-Based Rendering |
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323 | (10) |
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Using CoDeL to Rapidly Prototype Network Processsor Extensions |
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333 | (10) |
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Synchronous Transfer Architecture (STA) |
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343 | (10) |
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Generated DSP Cores for Implementation of an OFDM Communication System |
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353 | (10) |
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A Novel Data-Path for Accelerating DSP Kernels |
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363 | (10) |
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Scalable FFT Processors and Pipelined Butterfly Units |
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373 | (10) |
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Scalable Instruction-Level Parallelism |
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383 | (10) |
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A Low-Power Multithreaded Processor for Baseband Communication Systems |
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393 | (10) |
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Initial Evaluation of Multimedia Extensions on VLIW Architectures |
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403 | (10) |
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HIBI v.2 Communication Network for System-on-Chip |
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413 | (10) |
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SAMOS IV -- System Modeling, and Simulation |
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DIF: An Interchange Format for Dataflow-Based Design Tools |
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423 | (10) |
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Scalable and Modular Scheduling |
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433 | (10) |
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Early ISS Integration into Network-on-Chip Designs |
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443 | (10) |
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Cycle Accurate Simulation Model Generation for SoC Prototyping |
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453 | (10) |
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Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting |
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463 | (11) |
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A Communication-Centric Design Flow for HIBI-Based SoCs |
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474 | (10) |
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Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets |
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484 | (10) |
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Communication Optimization in Compaan Process Networks |
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494 | (13) |
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Analysis of Dataflow Programs with Interval-Limited Data-Rates |
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507 | (12) |
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High-Speed Event-Driven RTL Compiled Simulation |
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519 | (11) |
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A High-Level Programming Paradigm for SystemC |
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530 | (10) |
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Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications |
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540 | (10) |
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Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration |
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550 | (11) |
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| Author Index |
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561 | |
Other versions by this Author