High-Speed Cmos Circuits for Optical Receivers

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Format: Hardcover
Pub. Date: 2001-06-01
Publisher(s): Kluwer Academic Pub
List Price: $169.99

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Summary

The exponential growth of the number of internet nodes has suddenly created a widespread demand for high-speed optical and electronic devices, circuits, and systems. The new optical revolution has replaced modular, general-purpose building blocks by end-to-end solutions. Greater levels of integration on a single chip enable higher performance and lower cost. The mainstream VLSI technologies such as BiCmos and CMOS continue to take over the territories thus far claimed by GaAs and InP devices. This calls for an up-to-date book describing the design of high-speed electronic circuits for optical communication using modern techniques in a low-cost CMOS process. High-Speed CMOS Circuits for Optical Receivers covers the design of the world's first and second 10 Gb/s clock and data recovery circuits fabricated in a pure CMOS process. The second prototype meets some of the critical requirements recommended by the SONET OC-192 standard. The clock and data recovery circuits consume a power several times lower than in prototypes built in other fabrication processes. High-Speed CMOS Circuits for Optical Receivers describes novel techniques for implementation of such high-speed, high-performance circuits in a pure CMOS process. High-Speed CMOS Circuits for Optical Receivers is written for researchers and students interested in high-speed and mixed-mode circuit design with focus on CMOS circuit techniques. Designers working on various high-speed circuit projects for data communication, including optical com., giga bit ethernet will also find it of interest.

Table of Contents

List of Figuresp. vii
List of Tablesp. xi
Prefacep. xiii
Introductionp. 1
Overview of the Fiber Optic Networkp. 3
Overview of Fiber Optic Transceiversp. 5
Overview of Topicsp. 12
Tias and Limitersp. 13
TIAsp. 13
Limitersp. 16
Clock and Data Recovery Architecturesp. 21
Open-Loop CDR Architecturesp. 22
Phase-Locking CDR Architecturesp. 23
Full-Rate and Half-Rate Architecturesp. 27
Oscillatorsp. 29
General Theoryp. 29
Ring Oscillatorsp. 30
LC Oscillatorsp. 32
PLL Jitter Calculationp. 41
Phase Detectorsp. 42
Linear Phase Detectorsp. 45
Binary Phase Detectorsp. 48
Frequency Detectorsp. 52
Referenced Frequency Detectorsp. 53
Referenceless Frequency Detectorsp. 55
Decision Circuitsp. 58
A Cmos Interface for Detection of 1.2-GB/S Rz Datap. 61
Introductionp. 61
Matched Filteringp. 62
Architecturep. 65
Building Blocksp. 67
Low-Noise Wideband Amplifierp. 67
Integrate-and-Dump Circuitp. 69
Demultiplexerp. 71
Clock Bufferp. 73
Experimental Resultsp. 74
Conclusionp. 74
A 10-GB/S Linear Half-Rate Coms CDR Circuitp. 77
Architecturep. 77
Building Blocksp. 80
VCOp. 80
Phase Detectorp. 83
Charge Pump and Loop Filterp. 87
Experimental Resultsp. 89
Conclusionp. 92
A 10-GB/S Cmos CDR Circuit with Wide Capture Rangep. 95
Introductionp. 95
Architecturep. 97
Building Blocksp. 98
VCOp. 98
Phase and Frequency Detectorp. 102
Charge Pumpp. 106
Output Buffersp. 107
Loop Characterizationp. 108
Experimental Resultsp. 109
Conclusionp. 113
Conclusionp. 115
Referencesp. 119
Indexp. 123
Table of Contents provided by Syndetics. All Rights Reserved.

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