
High-Speed Cmos Circuits for Optical Receivers
by Savoj, Jafar; Razavi, BehzadRent Textbook
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Summary
Table of Contents
List of Figures | p. vii |
List of Tables | p. xi |
Preface | p. xiii |
Introduction | p. 1 |
Overview of the Fiber Optic Network | p. 3 |
Overview of Fiber Optic Transceivers | p. 5 |
Overview of Topics | p. 12 |
Tias and Limiters | p. 13 |
TIAs | p. 13 |
Limiters | p. 16 |
Clock and Data Recovery Architectures | p. 21 |
Open-Loop CDR Architectures | p. 22 |
Phase-Locking CDR Architectures | p. 23 |
Full-Rate and Half-Rate Architectures | p. 27 |
Oscillators | p. 29 |
General Theory | p. 29 |
Ring Oscillators | p. 30 |
LC Oscillators | p. 32 |
PLL Jitter Calculation | p. 41 |
Phase Detectors | p. 42 |
Linear Phase Detectors | p. 45 |
Binary Phase Detectors | p. 48 |
Frequency Detectors | p. 52 |
Referenced Frequency Detectors | p. 53 |
Referenceless Frequency Detectors | p. 55 |
Decision Circuits | p. 58 |
A Cmos Interface for Detection of 1.2-GB/S Rz Data | p. 61 |
Introduction | p. 61 |
Matched Filtering | p. 62 |
Architecture | p. 65 |
Building Blocks | p. 67 |
Low-Noise Wideband Amplifier | p. 67 |
Integrate-and-Dump Circuit | p. 69 |
Demultiplexer | p. 71 |
Clock Buffer | p. 73 |
Experimental Results | p. 74 |
Conclusion | p. 74 |
A 10-GB/S Linear Half-Rate Coms CDR Circuit | p. 77 |
Architecture | p. 77 |
Building Blocks | p. 80 |
VCO | p. 80 |
Phase Detector | p. 83 |
Charge Pump and Loop Filter | p. 87 |
Experimental Results | p. 89 |
Conclusion | p. 92 |
A 10-GB/S Cmos CDR Circuit with Wide Capture Range | p. 95 |
Introduction | p. 95 |
Architecture | p. 97 |
Building Blocks | p. 98 |
VCO | p. 98 |
Phase and Frequency Detector | p. 102 |
Charge Pump | p. 106 |
Output Buffers | p. 107 |
Loop Characterization | p. 108 |
Experimental Results | p. 109 |
Conclusion | p. 113 |
Conclusion | p. 115 |
References | p. 119 |
Index | p. 123 |
Table of Contents provided by Syndetics. All Rights Reserved. |
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