Reconfigurable Computing: Architectures, Tools and Applications : Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings
by Diniz, Pedro C.; Marques, Eduardo; Bertels, Koen; Fernandes, Marcio Merino; Cardoso, Joao M. P.Format: Paperback
Pub. Date: 2007-04-19
Publisher(s): Springer Verlag
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Summary
This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007. The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 were thoroughly reviewed and selected from 72 submissions. The papers are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications.
Table of Contents
| Architectures [Regular Papers] | |
| Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array | p. 1 |
| A Configurable Multi-ported Register File Architecture for Soft Processor Cores | p. 14 |
| MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture | p. 26 |
| Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture | p. 39 |
| Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs | p. 49 |
| Systematic Customization of On-Chip Crossbar Interconnects | p. 61 |
| Authentication of FPGA Bitstreams: Why and How | p. 73 |
| Architectures [Short Papers] | |
| Design of a Reversible PLD Architecture | p. 85 |
| Designing Heterogeneous FPGAs with Multiple SBs | p. 91 |
| Mapping Techniques and Tools [Regular Papers] | |
| Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations | p. 97 |
| Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware | p. 110 |
| Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations | p. 122 |
| A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions | p. 130 |
| Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping | p. 142 |
| The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining | p. 155 |
| Hardware/Software Codesign for Embedded Implementation of Neural Networks | p. 167 |
| Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues | p. 179 |
| Mapping Techniques and Tools [Short Papers] | |
| About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations | p. 191 |
| Arithmetic [Regular Papers] | |
| Switching Activity Models for Power Estimation in FPGA Multipliers | p. 201 |
| Multiplication over F[subscript p]m on FPGA: A Survey | p. 214 |
| A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm | p. 226 |
| A Fast Finite Field Multiplier | p. 238 |
| Applications [Regular Papers] | |
| Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval | p. 247 |
| Image Processing Architecture for Local Features Computation | p. 259 |
| A Compact Shader for FPGA-Based Volume Rendering Accelerators | p. 271 |
| Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications | p. 283 |
| FPGA-Accelerated Molecular Dynamics Simulations: An Overview | p. 293 |
| Reconfigurable Hardware Acceleration of Canonical Graph Labelling | p. 302 |
| Reconfigurable Computing for Accelerating Protein Folding Simulations | p. 314 |
| Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits | p. 326 |
| Applications [Short Papers] | |
| A Space Variant Mapping Architecture for Reliable Car Segmentation | p. 337 |
| A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads | p. 343 |
| Searching the Web with an FPGA Based Search Engine | p. 350 |
| An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma | p. 358 |
| Real Time Architectures for Moving-Objects Tracking | p. 365 |
| Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller | p. 373 |
| Multiple Sequence Alignment Using Reconfigurable Computing | p. 379 |
| Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing | p. 385 |
| Author Index | p. 391 |
| Table of Contents provided by Ingram. All Rights Reserved. |
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