VLSI Test Principles and Architectures,9780123705976

VLSI Test Principles and Architectures

by ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ISBN13: 9780123705976
ISBN10: 0123705975
Format: Hardcover
Pub. Date: 2006-07-07
Publisher(s): Elsevier Science
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Summary

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Preface xxi
In the Classroom xxiv
Acknowledgments xxv
Contributors xxvii
About the Editors xxix
Introduction
1(36)
Yinghua Min
Charles Stroud
Importance of Testing
1(1)
Testing During the VLSI Lifecycle
2(6)
VLSI Development Process
3(1)
Design Verification
4(1)
Yield and Reject Rate
5(1)
Electronic System Manufacturing Process
6(1)
System-Level Operation
6(2)
Challenges in VLSI Testing
8(14)
Test Generation
9(2)
Fault Models
11(1)
Stuck-At Faults
12(3)
Transistor Faults
15(1)
Open and Short Faults
16(3)
Delay Faults and Crosstalk
19(1)
Pattern Sensitivity and Coupling Faults
20(1)
Analog Fault Models
21(1)
Levels of Abstraction in VLSI Testing
22(3)
Register-Transfer Level and Behavioral Level
22(1)
Gate Level
23(1)
Switch Level
24(1)
Physical Level
24(1)
Historical Review of VLSI Test Technology
25(8)
Automatic Test Equipment
25(2)
Automatic Test Pattern Generation
27(1)
Fault Simulation
28(1)
Digital Circuit Testing
28(1)
Analog and Mixed-Signal Circuit Testing
29(1)
Design for Testability
29(2)
Board Testing
31(1)
Boundary Scan Testing
32(1)
Concluding Remarks
33(1)
Exercises
33(4)
Acknowledgments
34(1)
References
34(3)
Design for Testability
37(68)
Laung-Terng (L.-T.) Wang
Xiaoqing Wen
Khader S. Abdel-Hafez
Introduction
37(3)
Testability Analysis
40(10)
SCOAP Testability Analysis
41(1)
Combinational Controllability and Observability Calculation
41(2)
Sequential Controllability and Observability Calculation
43(2)
Probability-Based Testability Analysis
45(2)
Simulation-Based Testability Analysis
47(1)
RTL Testability Analysis
48(2)
Design for Testability Basics
50(5)
Ad Hoc Approach
51(1)
Test Point Insertion
51(2)
Structured Approach
53(2)
Scan Cell Designs
55(4)
Muxed-D Scan Cell
55(1)
Clocked-Scan Cell
56(1)
LSSD Scan Cell
57(2)
Scan Architectures
59(11)
Full-Scan Design
59(1)
Muxed-D Full-Scan Design
59(3)
Clocked Full-Scan Design
62(1)
LSSD Full-Scan Design
62(2)
Partial-Scan Design
64(3)
Random-Access Scan Design
67(3)
Scan Design Rules
70(6)
Tristate Buses
71(1)
Bidirectional I/O Ports
71(1)
Gated Clocks
71(3)
Derived Clocks
74(1)
Combinational Feedback Loops
74(1)
Asynchronous Set/Reset Signals
75(1)
Scan Design Flow
76(11)
Scan Design Rule Checking and Repair
77(1)
Scan Synthesis
78(1)
Scan Configuration
79(3)
Scan Replacement
82(1)
Scan Reordering
82(1)
Scan Stitching
83(1)
Scan Extraction
83(1)
Scan Verification
84(1)
Verifying the Scan Shift Operation
85(1)
Verifying the Scan Capture Operation
86(1)
Scan Design Costs
86(1)
Special-Purpose Scan Designs
87(5)
Enhanced Scan
87(1)
Snapshot Scan
88(2)
Error-Resilient Scan
90(2)
RTL Design for Testability
92(3)
RTL Scan Design Rule Checking and Repair
93(1)
RTL Scan Synthesis
94(1)
RTL Scan Extraction and Scan Verification
95(1)
Concluding Remarks
95(1)
Exercises
96(9)
Acknowledgments
99(1)
References
99(6)
Logic and Fault Simulation
105(56)
Jiun-Lang Huang
James C.-M. Li
Duncan M. (Hank) Walker
Introduction
106(2)
Logic Simulation for Design Verification
106(1)
Fault Simulation for Test and Diagnosis
107(1)
Simulation Models
108(13)
Gate-Level Network
109(1)
Sequential Circuits
109(1)
Logic Symbols
110(1)
Unknown State u
111(2)
High-Impedance State Z
113(1)
Intermediate Logic States
114(1)
Logic Element Evaluation
114(1)
Truth Tables
115(1)
Input Scanning
115(1)
Input Counting
116(1)
Parallel Gate Evaluation
116(2)
Timing Models
118(1)
Transport Delay
118(1)
Inertial Delay
119(1)
Wire Delay
119(1)
Functional Element Delay Model
120(1)
Logic Simulation
121(11)
Compiled-Code Simulation
121(1)
Logic Optimization
121(2)
Logic Levelization
123(1)
Code Generation
124(1)
Event-Driven Simulation
125(1)
Nominal-Delay Event-Driven Simulation
126(3)
Compiled-Code Versus Event-Driven Simulation
129(1)
Hazards
130(1)
Static Hazard Detection
131(1)
Dynamic Hazard Detection
132(1)
Fault Simulation
132(22)
Serial Fault Simulation
133(2)
Parallel Fault Simulation
135(1)
Parallel Fault Simulation
135(2)
Parallel-Pattern Fault Simulation
137(2)
Deductive Fault Simulation
139(4)
Concurrent Fault Simulation
143(3)
Differential Fault Simulation
146(2)
Fault Detection
148(1)
Comparison of Fault Simulation Techniques
149(2)
Alternatives to Fault Simulation
151(1)
Toggle Coverage
151(1)
Fault Sampling
151(1)
Critical Path Tracing
152(1)
Statistical Fault Analysis
153(1)
Concluding Remarks
154(1)
Exercises
155(6)
References
158(3)
Test Generation
161(102)
Michael S. Hsiao
Introduction
161(2)
Random Test Generation
163(3)
Exhaustive Testing
166(1)
Theoretical Background: Boolean Difference
166(3)
Untestable Faults
168(1)
Designing a Stuck-At ATPG for Combinational Circuits
169(25)
A Naive ATPG Algorithm
169(3)
Backtracking
172(1)
A Basic ATPG Algorithm
173(4)
D Algorithm
177(5)
PODEM
182(4)
FAN
186(1)
Static Logic Implications
187(4)
Dynamic Logic Implications
191(3)
Designing a Sequential ATPG
194(6)
Time Frame Expansion
194(2)
5-Valued Algebra Is Insufficient
196(1)
Gated Clocks and Multiple Clocks
197(3)
Untestable Fault Identification
200(7)
Multiple-Line Conflict Analysis
203(4)
Designing a Simulation-Based ATPG
207(11)
Overview
208(1)
Genetic-Algorithm-Based ATPG
208(4)
Issues Concerning the GA Population
212(1)
Issues Concerning GA Parameters
213(1)
Issues Concerning the Fitness Function
213(2)
CASE Studies
215(3)
Advanced Simulation-Based ATPG
218(8)
Seeding the GA with Helpful Sequences
218(4)
Logic-Simulation-Based ATPG
222(3)
Spectrum-Based ATPG
225(1)
Hybrid Deterministic and Simulation-Based ATPG
226(5)
ALT-TEST Hybrid
228(3)
ATPG for Non-Stuck-At Faults
231(15)
Designing an ATPG That Captures Delay Defects
231(2)
Classification of Path-Delay Faults
233(3)
ATPG for Path-Delay Faults
236(2)
ATPG for Transition Faults
238(2)
Transition ATPG Using Stuck-At ATPG
240(1)
Transition ATPG Using Stuck-At Vectors
240(1)
Transition Test Chains via Weighted Transition Graph
241(3)
Bridging Fault ATPG
244(2)
Other Topics in Test Generation
246(2)
Test Set Compaction
246(1)
N-Detect ATPG
247(1)
ATPG for Acyclic Sequential Circuits
247(1)
IDDQ Testing
247(1)
Designing a High-Level ATPG
248(1)
Concluding Remarks
248(1)
Exercises
249(14)
References
256(7)
Logic Built-In Self-Test
263(78)
Laung-Terng (L.-T.) Wang
Introduction
264(2)
BIST Design Rules
266(5)
Unknown Source Blocking
267(1)
Analog Blocks
267(1)
Memories and Non-Scan Storage Elements
268(1)
Combinational Feedback Loops
268(1)
Asynchronous Set/Reset Signals
268(1)
Tristate Buses
269(1)
False Paths
270(1)
Critical Paths
270(1)
Multiple-Cycle Paths
270(1)
Floating Ports
270(1)
Bidirectional I/O Ports
271(1)
Re-Timing
271(1)
Test Pattern Generation
271(19)
Exhaustive Testing
275(1)
Binary Counter
275(1)
Complete LFSR
275(2)
Pseudo-Random Testing
277(1)
Maximum-Length LFSR
278(1)
Weighted LFSR
278(1)
Cellular Automata
278(3)
Pseudo-Exhaustive Testing
281(1)
Verification Testing
282(5)
Segmentation Testing
287(1)
Delay Fault Testing
288(1)
Summary
289(1)
Output Response Analysis
290(6)
Ones Count Testing
291(1)
Transition Count Testing
291(1)
Signature Analysis
292(1)
Serial Signature Analysis
292(2)
Parallel Signature Analysis
294(2)
Logic BIST Architectures
296(8)
BIST Architectures for Circuits without Scan Chains
296(1)
A Centralized and Separate Board-Level BIST Architecture
296(1)
Built-In Evaluation and Self-Test (BEST)
297(1)
BIST Architectures for Circuits with Scan Chains
297(1)
LSSD On-Chip Self-Test
297(1)
Self-Testing Using MISR and Parallel SRSG
298(1)
BIST Architectures Using Register Reconfiguration
298(1)
Built-In Logic Block Observer
299(1)
Modified Built-In Logic Block Observer
300(1)
Concurrent Built-In Logic Block Observer
300(2)
Circular Self-Test Path (CSTP)
302(1)
BIST Architectures Using Concurrent Checking Circuits
303(1)
Concurrent Self-Verification
303(1)
Summary
304(1)
Fault Coverage Enhancement
304(6)
Test Point Insertion
305(1)
Test Point Placement
306(1)
Control Point Activation
307(1)
Mixed-Mode BIST
308(1)
ROM Compression
308(1)
LFSR Reseeding
308(1)
Embedding Deterministic Patterns
309(1)
Hybrid BIST
309(1)
BIST Timing Control
310(9)
Single-Capture
310(1)
One-Hot Single-Capture
310(1)
Staggered Single-Capture
311(1)
Skewed-Load
311(1)
One-Hot Skewed-Load
312(1)
Aligned Skewed-Load
312(2)
Staggered Skewed-Load
314(1)
Double-Capture
315(1)
One-Hot Double-Capture
315(1)
Aligned Double-Capture
316(1)
Staggered Double-Capture
317(1)
Fault Detection
317(2)
A Design Practice
319(8)
BIST Rule Checking and Violation Repair
320(1)
Logic BIST System Design
320(1)
Logic BIST Architecture
320(1)
TPG and ORA
321(1)
Test Controller
322(1)
Clock Gating Block
323(2)
Re-Timing Logic
325(1)
Fault Coverage Enhancing Logic and Diagnostic Logic
325(1)
RTL BIST Synthesis
326(1)
Design Verification and Fault Coverage Enhancement
326(1)
Concluding Remarks
327(1)
Exercises
327(14)
Acknowledgments
331(1)
References
331(10)
Test Compression
341(56)
Xiaowei Li
Kuen-Jong Lee
Nur A. Touba
Introduction
342(2)
Test Stimulus Compression
344(20)
Code-Based Schemes
345(1)
Dictionary Code (Fixed-to-Fixed)
345(1)
Huffman Code (Fixed-to-Variable)
346(3)
Run-Length Code (Variable-to-Fixed)
349(1)
Golomb Code (Variable-to-Variable)
350(1)
Linear-Decompression-Based Schemes
351(4)
Combinational Linear Decompressors
355(1)
Fixed-Length Sequential Linear Decompressors
355(1)
Variable-Length Sequential Linear Decompressors
356(1)
Combined Linear and Nonlinear Decompressors
357(2)
Broadcast-Scan-Based Schemes
359(1)
Broadcast Scan
359(1)
Illinois Scan
360(2)
Multiple-Input Broadcast Scan
362(1)
Reconfigurable Broadcast Scan
362(1)
Virtual Scan
363(1)
Test Response Compaction
364(12)
Space Compaction
367(1)
Zero-Aliasing Linear Compaction
367(2)
X-Compact
369(2)
X-Blocking
371(1)
X-Masking
372(1)
X-Impact
373(1)
Time Compaction
374(1)
Mixed Time and Space Compaction
375(1)
Industry Practices
376(12)
OPMISR+
377(2)
Embedded Deterministic Test
379(3)
VirtualScan and UltraScan
382(3)
Adaptive Scan
385(1)
ETCompression
386(2)
Summary
388(1)
Concluding Remarks
388(1)
Exercises
389(8)
Acknowledgments
390(1)
References
391(6)
Logic Diagnosis
397(64)
Shi-Yu Huang
Introduction
397(4)
Combinational Logic Diagnosis
401(26)
Cause--Effect Analysis
401(2)
Compaction and Compression of Fault Dictionary
403(2)
Effect--Cause Analysis
405(2)
Structural Pruning
407(1)
Backtrace Algorithm
408(1)
Inject-and-Evaluate Paradigm
409(9)
Chip-Level Strategy
418(1)
Direct Partitioning
418(2)
Two-Phase Strategy
420(4)
Overall Chip-Level Diagnostic Flow
424(1)
Diagnostic Test Pattern Generation
425(1)
Summary of Combinational Logic Diagnosis
426(1)
Scan Chain Diagnosis
427(15)
Preliminaries for Scan Chain Diagnosis
427(3)
Hardware-Assisted Method
430(2)
Modified Inject-and-Evaluate Paradigm
432(2)
Signal-Profiling-Based Method
434(1)
Diagnostic Test Sequence Selection
434(1)
Run-and-Scan Test Application
434(1)
Why Functional Sequence?
435(2)
Profiling-Based Analysis
437(4)
Summary of Scan Chain Diagnosis
441(1)
Logic BIST Diagnosis
442(7)
Overview of Logic BIST Diagnosis
442(1)
Interval-Based Methods
443(3)
Masking-Based Methods
446(3)
Concluding Remarks
449(1)
Exercises
450(11)
Acknowledgments
453(1)
References
454(7)
Memory Testing and Built-In Self-Test
461(56)
Cheng-Wen Wu
Introduction
462(1)
RAM Functional Fault Models and Test Algorithms
463(12)
RAM Functional Fault Models
463(2)
RAM Dynamic Faults
465(1)
Functional Test Patterns and Algorithms
466(3)
March Tests
469(2)
Comparison of RAM Test Patterns
471(2)
Word-Oriented Memory
473(1)
Multi-Port Memory
473(2)
RAM Fault Simulation and Test Algorithm Generation
475(13)
Fault Simulation
476(1)
RAMSES
477(3)
Test Algorithm Generation by Simulation
480(8)
Memory Built-In Self-Test
488(20)
RAM Specification and BIST Design Strategy
489(4)
BIST Architectures and Functions
493(2)
BIST Implementation
495(5)
BRAINS: A RAM BIST Compiler
500(8)
Concluding Remarks
508(1)
Exercises
509(8)
Acknowledgments
513(1)
References
513(4)
Memory Diagnosis and Built-In Self-Repair
517(40)
Cheng-Wen Wu
Introduction
518(1)
Why Memory Diagnosis?
518(1)
Why Memory Repair?
518(1)
Refined Fault Models and Diagnostic Test Algorithms
518(3)
BIST with Diagnostic Support
521(5)
Controller
521(2)
Test Pattern Generator
523(1)
Fault Site Indicator (FSI)
524(2)
RAM Defect Diagnosis and Failure Analysis
526(3)
RAM Redundancy Analysis Algorithms
529(8)
Conventional Redundancy Analysis Algorithms
529(2)
The Essential Spare Pivoting Algorithm
531(4)
Repair Rate and Overhead
535(2)
Built-In Self-Repair
537(15)
Redundancy Organization
537(1)
BISR Architecture and Procedure
538(3)
BIST Module
541(1)
BIRA Module
542(3)
An Industrial Case
545(3)
Repair Rate and Yield
548(4)
Concluding Remarks
552(1)
Exercises
552(5)
Acknowledgments
553(1)
References
553(4)
Boundary Scan and Core-Based Testing
557(62)
Kuen-Jong Lee
Introduction
558(3)
IEEE 1149 Standard Family
558(1)
Core-Based Design and Test Considerations
559(2)
Digital Boundary Scan (IEEE Std. 1149.1)
561(18)
Basic Concept
561(1)
Overall 1149.1 Test Architecture and Operations
562(2)
Test Access Port and Bus Protocols
564(1)
Data Registers and Boundary-Scan Cells
565(2)
TAP Controller
567(2)
Instruction Register and Instruction Set
569(5)
Boundary-Scan Description Language
574(1)
On-Chip Test Support with Boundary Scan
574(2)
Board and System-Level Boundary-Scan Control Architectures
576(3)
Boundary Scan for Advanced Networks (IEEE 1149.6)
579(6)
Rationale for 1149.6
579(2)
1149.6 Analog Test Receiver
581(1)
1149.6 Digital Driver Logic
581(1)
1149.6 Digital Receiver Logic
582(2)
1149.6 Test Access Port (TAP)
584(1)
Summary
585(1)
Embedded Core Test Standard (IEEE Std. 1500)
585(25)
SOC (System-on-Chip) Test Problems
585(2)
Overall Architecture
587(2)
Wrapper Components and Functions
589(8)
Instruction Set
597(4)
Core Test Language (CTL)
601(2)
Core Test Supporting and System Test Configurations
603(3)
Hierarchical Test Control and Plug-and-Play
606(4)
Comparisons between the 1500 and 1149.1 Standards
610(1)
Concluding Remarks
611(1)
Exercises
612(7)
Acknowledgments
614(1)
References
614(5)
Analog and Mixed-Signal Testing
619(60)
Chauchin Su
Introduction
619(8)
Analog Circuit Properties
620(1)
Continuous Signals
621(1)
Large Range of Circuits
621(1)
Nonlinear Characteristics
621(1)
Feedback Ambiguity
622(1)
Complicated Cause--Effect Relationship
622(1)
Absence of Suitable Fault Model
622(1)
Requirement for Accurate Instruments for Measuring Analog Signals
623(1)
Analog Defect Mechanisms and Fault Models
623(2)
Hard Faults
625(1)
Soft Faults
625(2)
Analog Circuit Testing
627(14)
Analog Test Approaches
627(2)
Analog Test Waveforms
629(2)
DC Parametric Testing
631(1)
Open-Loop Gain Measurement
632(1)
Unit Gain Bandwidth Measurement
633(1)
Common Mode Rejection Ratio Measurement
634(1)
Power Supply Rejection Ratio Measurement
635(1)
AC Parametric Testing
635(1)
Maximal Output Amplitude Measurement
636(1)
Frequency Response Measurement
637(2)
SNR and Distortion Measurement
639(2)
Intermodulation Distortion Measurement
641(1)
Mixed-Signal Testing
641(17)
Introduction to Analog--Digital Conversion
642(2)
ADC and DAC Circuit Structure
644(2)
DAC Circuit Structure
646(1)
ADC Circuit Structure
646(1)
ADC/DAC Specification and Fault Models
647(5)
IEEE 1057 Standard
652(2)
Time-Domain ADC Testing
654(1)
Code Bins
654(1)
Code Transition Level Test (Static)
655(1)
Code Transition Level Test (Dynamic)
655(1)
Gain and Offset Test
656(1)
Linearity Error and Maximal Static Error
657(1)
Sine Wave Curve-Fit Test
658(1)
Frequency-Domain ADC Testing
658(1)
IEEE 1149.4 Standard for a Mixed-Signal Test Bus
658(15)
IEEE 1149.4 Overview
659(1)
Scope of the Standard
660(1)
IEEE 1149.4 Circuit Structures
661(4)
IEEE 1149.4 Instructions
665(1)
Mandatory Instructions
665(1)
Optional Instructions
665(1)
IEEE 1149.4 Test Modes
666(1)
Open/Short Interconnect Testing
666(1)
Extended Interconnect Measurement
667(4)
Complex Network Measurement
671(1)
High-Performance Configuration
672(1)
Concluding Remarks
673(1)
Exercises
673(6)
Acknowledgments
676(1)
References
677(2)
Test Technology Trends in the Nanometer Age
679(72)
Kwang-Ting (Tim) Cheng
Wen-Ben Jone
Laung-Terng (L.-T.) Wang
Test Technology Roadmap
680(5)
Delay Testing
685(7)
Test Application Schemes for Testing Delay Defects
686(1)
Delay Fault Models
687(3)
Summary
690(2)
Coping with Physical Failures, Soft Errors, and Reliability Issues
692(14)
Signal Integrity and Power Supply Noise
692(1)
Integrity Loss Fault Model
693(1)
Location
694(1)
Pattern Generation
694(1)
Sensing and Readout
695(1)
Parametric Defects, Process Variations, and Yield
696(1)
Defect-Based Test
697(1)
Soft Errors
698(3)
Fault Tolerance
701(4)
Defect and Error Tolerance
705(1)
FPGA Testing
706(5)
Impact of Programmability
706(2)
Testing Approaches
708(1)
Built-In Self-Test of Logic Resources
708(1)
Built-In Self-Test of Routing Resources
709(1)
Recent Trends
710(1)
MEMS Testing
711(8)
Basic Concepts for Capacitive MEMS Devices
711(2)
MEMS Built-In Self-Test
713(1)
Sensitivity BIST Scheme
713(1)
Symmetry BIST Scheme
713(1)
A Dual-Mode BIST Technique
714(2)
A BIST Example for MEMS Comb Accelerometers
716(3)
Conclusions
719(1)
High-speed I/O Testing
719(9)
I/O Interface Technology and Trend
720(4)
I/O Testing and Challenges
724(1)
High-Performance I/O Test Solutions
725(1)
Future Challenges
726(2)
RF Testing
728(9)
Core RF Building Blocks
729(1)
RF Test Specifications and Measurement Procedures
730(1)
Gain
730(1)
Conversion Gain
731(1)
Third-Order Intercept
731(2)
Noise Figure
733(1)
Tests for System-Level Specifications
733(1)
Adjacent Channel Power Ratio
733(1)
Error Vector Magnitude, Magnitude Error, and Phase Error
734(1)
Current and Future Trends
735(1)
Future Trends
736(1)
Concluding Remarks
737(14)
Acknowledgments
738(1)
References
738(13)
Index 751

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